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LTC3868 3868fb typical a pplica t ion fea t ures a pplica t ions descrip t ion low i q , dual 2-phase synchronous step-down controller high effciency dual 8.5v/3.3v step-down converter n low operating i q : 170a (one channel on) n wide output voltage range: 0.8v v out 14v n wide v in range: 4v to 24v n r sense or dcr current sensing n out-of-phase controllers reduce required input capacitance and power supply induced noise n opti-loop ? compensation minimizes c out n phase-lockable frequency (75khz to 850khz) n programmable fixed frequency (50khz to 900khz) n selectable continuous, pulse-skipping or burst mode ? operation at light loads n very low dropout operation: 99% duty cycle n adjustable output voltage soft-start n power good output voltage monitor n output overvoltage protection n output latchoff protection during short circuit n low shutdown i q : 8a n internal ldo powers gate drive from v in or extv cc n no current foldback during start-up n small 5mm 5mm qfn package n notebook and palmtop computers n portable instruments n battery operated digital devices n distributed dc power systems l, lt, ltc, ltm, burst mode, opti-loop, polyphase, module, linear technology and the linear logo are registered trademarks and no r sense and ultrafast are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. effciency and power loss vs load current the ltc ? 3868 is a high performance dual step-down switching regulator controller that drives all n-channel synchronous power mosfet stages. a constant frequency current mode architecture allows a phase-lockable fre - quency of up to 850khz. power loss and noise due to the input capacitor esr are minimized by operating the two controller outputs out of phase. the 170a no-load quiescent current extends operating life in battery-powered systems. opti-loop compensa - tion allows the transient response to be optimized over a wide range of output capacitance and esr values. the LTC3868 features a precision 0.8v reference and a power good output indicator. a wide 4v to 24v input supply range encompasses a wide range of intermediate bus voltages and battery chemistries. independent soft-start pins for each controller ramp the output voltages during start-up. current foldback limits mosfet heat dissipation during short-circuit conditions. the output short-circuit latchoff feature further protects the circuit in short-circuit conditions. for a leaded 28-lead ssop package with a fxed current limit and one pgood output, without phase modulation or a clock output, see the LTC3868-1 data sheet. 0.1f 62.5k 3.3h 680pf 150f 4.7f 22f 50v 0.007 20k 15k v out1 3.3v 5a 150f 0.1f 193k 7.2h 680pf 0.01 20k 15k v out2 8.5v 3.5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd sense1 + sense2 + sense1 ? sense2 ? v fb1 v fb2 i th1 i th2 v in intv cc ss1 ss2 v in 9v to 24v 3868 ta01 0.1f 0.1f LTC3868 output current (a) 0.0001 40 efficiency (%) power loss (mw) 50 60 70 80 0.001 0.01 0.1 1 10 3868 ta01b 30 20 10 0 90 100 10 100 1000 1 0.1 10000 efficiency power loss v in = 12v v out = 3.3v figure 12 circuit
LTC3868 3868fb p in c on f igura t ion a bsolu t e maxi m u m r a t ings (note 1) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 top view sense1 ? freq phasmd clkout pllin/mode sgnd run1 run2 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sense1 + v fb1 i th1 ss1 i lim pgood1 tg1 sw1 sense2 ? sense2 + v fb2 i th2 ss2 pgood2 tg2 sw2 uh package 32-lead (5mm s 5mm) plastic qfn 33 sgnd t jmax = 125c, q ja = 34c/w exposed pad (pin 33) is sgnd, must be soldered to pcb or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3868euh#pbf LTC3868euh#trpbf 3868 3 2 -lead (5mm s 5 mm) plastic qfn C40c to 85c LTC3868iuh#pbf LTC3868iuh#trpbf 3868 3 2 -lead (5mm s 5 mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container.consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ f o r more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ input supply voltage (v in ) ......................... C0.3v to 28v topside driver voltages boost1, boost2 ................................. C0.3v to 34v switch voltage (sw1, sw2) ........................ C5v to 28v (boost1-sw1), (boost2-sw2) ................ C0.3v to 6v run1, run2 ................................................ C0.3v to 8v maximum current sourced into pin from source >8v ...................................................... 100a sense1 + , sense2 + , sense1 C sense2 C voltages ...................................... C0.3v to 16v pllin/mode, freq voltages .............. C0.3v to intv cc i lim , phasmd voltages ....................... C0.3v to intv cc extv cc ...................................................... C0.3v to 14v i th1 , i th2 ,v fb1 , v fb2 voltages ...................... C0.3v to 6v pgood1, pgood2 voltages ....................... C0.3v to 6v ss1, ss2, intv cc voltages ......................... C0.3v to 6v operating temperature range (note 2) ... C40c to 85c junction temperature (note 3) ............................. 125c storage temperature range ................... C65c to 150c e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in input supply operating voltage range 4 24 v v fb1,2 regulated feedback voltage (note 4) i th1,2 voltage = 1.2v l 0.788 0.8 0.812 v i fb1,2 feedback current (note 4) 5 50 na v reflnreg reference voltage line regulation (note 4) v in = 4.5v to 24v 0.002 0.02 %/v v loadreg output voltage load regulation (note4) me asured in servo loop, i th voltage = 1.2v to 0.7v l 0.01 0.1 % (note4) m e asured in servo loop, i th voltage = 1.2v to 2v l C0.01 C0.1 % the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted.
LTC3868 3868fb symbol parameter conditions min typ max units g m1,2 transconductance amplifer g m (note 4) i th1,2 = 1.2v, sink/source = 5a 2 mmho i q input dc supply current (note 5) pulse-skipping or forced continuous mode (o ne channel on) run1 = 5v and run2 = 0v or r u n1 = 0v and run2 = 5v, v fb1 = 0.83v (no load) 1.3 ma p u lse-skipping or forced continuous mode ( b oth channels on) run1,2 = 5v, v fb1,2 = 0.83v (no load) 2 ma sl eep mode (one channel on) run1 = 5v and run2 = 0v or r u n1 = 0v and run2 = 5v, v fb1 = 0.83v (no load) 170 250 a s l eep mode (both channels on) run1,2 = 5v, v fb1,2 = 0.83v (no load) 300 450 a shutdown r u n1,2 = 0v 8 25 a uvlo u n dervoltage lockout intv cc ramping up intv cc ramping down l l 3.6 4 3.8 4.2 4 v v v ovl feedback overvoltage protection measured at v fb1,2 , relative to regulated v fb1,2 7 10 13 % i sense + sense + pins current each channel 1 a i sense C sense C pins current each channel v out1,2 < intv cc C 0.5v v out1,2 > intv cc + 0.5v 540 1 700 a a df max maximum duty factor in dropout, freq = 0v 98 99.4 % i ss1,2 soft-start charge current v ss1,2 = 0v 0.7 1.0 1.4 a v run1,2 on run pin on threshold v run1 , v run2 rising l 1.21 1.26 1.31 v v run1,2 hyst run pin hysteresis 50 mv v ss1,2 la ss pin latchoff arming threshold v ss1 , v ss2 rising from 1v 1.9 2 2.1 v v ss1,2 lt ss pin latchoff threshold v ss1 , v ss2 falling from 2v 1.3 1.5 1.7 v i dsc1,2 lt ss discharge current short-circuit condition v fb1,2 = 0.5v, v ss1,2 = 4.5v 7 10 13 a v sense(max) maximum current sense threshold v fb1,2 = 0.7v, v sense1 C, 2 C = 3.3v, i lim = 0 v fb1,2 = 0.7v, v sense1 C, 2 C = 3.3v, i lim = float v fb1,2 = 0.7v, v sense1 C, 2 C = 3.3v, i lim = intv cc 22 43 64 30 50 75 36 57 86 mv mv mv gate driver tg1,2 pu ll-up on-resistance pu ll-down on-resistance 2.5 1.5 bg1,2 pu ll-up on-resistance pu ll-down on-resistance 2.4 1.1 tg 1,2 t r tg1,2 t f tg transition time: r ise time f all t ime (note 6) c load = 3300pf c load = 3300pf 25 16 ns ns b g 1,2 t r bg1,2 t f bg transition time: r ise time f all time (note 6) c load = 3300pf c load = 3300pf 28 13 ns ns tg /bg t 1d top gate off to bottom gate on delay sy nchronous switch-on delay time c load = 3300pf each driver 30 ns bg /tg t 1d bottom gate off to top gate on delay to p switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 95 ns e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted.
LTC3868 3868fb e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, v run1,2 = 5v, extv cc = 0v unless otherwise noted. symbol parameter conditions min typ max units intv cc linear regulator v intvccvin internal v cc voltage 6v < v in < 24v, v extvcc = 0v 4.85 5.1 5.35 v v ldovin intv cc load regulation i cc = 0ma to 50ma, v extvcc = 0v 0.7 1.1 % v intvccext internal v cc voltage 6v < v extvcc < 13v 4.85 5.1 5.35 v v ldoext intv cc load regulation i cc = 0ma to 50ma, v extvcc = 8.5v 0.6 1.1 % v extvcc extv cc switchover voltage extv cc ramping positive 4.5 4.7 4.9 v v ldohys extv cc hysteresis 250 mv oscillator and phase-locked loop f 25k programmable frequency r freq = 25k, pllin/mode = dc voltage 105 khz f 65k programmable frequency r freq = 65k, pllin/mode = dc voltage 375 440 505 khz f 105k programmable frequency r freq = 105k, pllin/mode = dc voltage 835 khz f low low fixed frequency v freq = 0v, pllin/mode = dc voltage 320 350 380 khz f high high fixed frequency v freq = intv cc , pllin/mode = dc voltage 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pgood1 and pgood2 outputs v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative h ysteresis C13 C10 2.5 C7 % % v fb with respect to set regulated voltage v fb ramping positive h ysteresis 7 10 2.5 13 % % t pg delay for reporting a fault (pgood low) 25 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum ratings for extended periods may affect device reliability and lifetime. note 2: the LTC3868e is guaranteed to meet performance specifcations from 0c to 85c. specifcations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3868i is guaranteed over the full C40c to 85c operating temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 34c/w) note 4: the LTC3868 is tested in a feedback loop that servos v ith1,2 to a specifed voltage and measures the resultant v fb1,2 . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specifed for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section).
LTC3868 3868fb typical p er f or m ance c harac t eris t ics effciency and power loss vs output current effciency vs output current load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load soft start-up effciency vs input voltage output current (a) 0.0001 40 efficiency (%) 50 60 70 80 0.001 0.01 0.1 1 10 3868 g02 30 20 10 0 90 100 v in = 5v v in = 12v v out = 3.3v figure 12 circuit input voltage (v) 0 efficiency (%) 90 92 94 3868 g03 88 86 84 80 10 20 5 15 25 28 82 98 96 figure 12 circuit v out = 3.3v i out = 4a output current (a) 0.0001 40 efficiency (%) power loss (mw) 50 60 70 80 0.001 0.01 0.1 1 10 3868 g01 30 20 10 0 90 100 10 100 1000 1 0.1 10000 figure 12 circuit v in = 12v v out = 3.3v burst mode operation pulse- skipping fcm v out 100mv/div ac- coupled i l 2a/div 20s/div 3868 g04 v out = 3.3v figure 12 circuit v out 100mv/div ac- coupled i l 2a/div 20s/div 3868 g05 v out = 3.3v figure 12 circuit v out 100mv/div ac- coupled i l 2a/div 20s/div 3868 g06 v out = 3.3v figure 12 circuit burst mode operation 2a/div forced continuous mode pulse- skipping mode 2s/div 3868 g07 v out = 3.3v i load = 200a figure 12 circuit v out2 2v/div v out1 2v/div 20ms/div 3868 g08 figure 12 circuit
LTC3868 3868fb typical p er f or m ance c harac t eris t ics total input supply current vs input voltage extv cc switchover and intv cc voltages vs temperature intv cc line regulation maximum current sense voltage vs i th voltage sense C pin input bias current maximum current sense threshold vs duty cycle foldback current limit quiescent current vs temperature shutdown current vs temperature input voltage (v) 5 supply current (a) 350 20 3868 g10 200 100 10 15 25 28 50 0 400 300 250 150 300a load figure 12 circuit v out = 3.3v one channel on no load temperature (c) ?45 extv cc and intv cc voltage (v) 5.4 30 3868 g11 4.8 4.4 ?20 5 55 4.2 4.0 5.6 5.2 5.0 4.6 80 105 130 intv cc extv cc rising extv cc falling input voltage (v) 0 5.0 intv cc voltage (v) 5.1 5.1 5.2 5.2 5 10 15 20 3868 g12 25 28 v sense common mode voltage (v) 0 ?600 sense ? current (a) ?500 ?550 ?450 ?400 ?300 ?350 ?200 ?250 0 5 10 15 3868 g14 ?50 ?100 ?150 feedback voltage (v) 0 0 maximum current sense voltage (mv) 10 30 40 50 0.6 90 3868 g16 20 0.3 0.1 0.7 0.4 0.2 0.8 0.5 0.9 60 70 80 i lim = intv cc i lim = float i lim = gnd i th pin voltage 0 current sense threshold (mv) 40 60 80 0.6 1.0 3868 g13 20 0 0.2 0.4 0.8 1.2 1.4 ?20 ?40 pulse-skipping forced continuous burst mode operation (falling) burst mode operation (rising) i lim = gnd i lim = float i lim = intv cc 5% duty cycle duty cycle (%) 0 maximum current sense voltage (mv) 40 60 80 3868 g15 20 0 20 40 50 100 80 60 10 30 90 70 i lim = intv cc i lim = float i lim = gnd temperature (c) ?45 110 quiescent current (a) 120 190 200 240 220 ?20 30 55 130 3868 g17 230 210 150 160 130 140 180 170 5 80 105 pllin/mode = 0 v in = 12v v out = 3.3v one channel on temperature (c) ?45 shutdown current (a) 8 9 10 30 80 3868 g18 7 6 ?20 5 55 105 130 5 4
LTC3868 3868fb typical p er f or m ance c harac t eris t ics soft-start pull-up current vs temperature shutdown (run) threshold vs temperature regulated feedback voltage vs temperature sense C pin input current vs temperature shutdown current vs input voltage oscillator frequency vs temperature undervoltage lockout threshold vs temperature temperature (c) ?45 ss pull-up current (a) 1.15 30 3868 g19 1.00 0.90 ?20 5 55 0.85 0.80 1.20 1.10 1.05 0.95 80 105 130 temperature (c) ?45 0.90 run pin voltage (v) 0.95 1.05 1.10 1.15 1.40 1.25 5 55 80 3868 g20 1.00 1.30 1.35 1.20 ?20 30 105 130 temperature (c) ?45 regulated feedback voltage (mv) 806 30 3868 g21 800 796 ?20 5 55 794 792 808 804 802 798 80 105 130 temperature (c) ?45 ?600 sense ? current (a) ?550 ?200 ?150 50 ?50 ?20 30 55 130 3868 g22 0 ?100 ?400 ?350 ?500 ?450 ?250 ?300 5 80 105 v out = 3.3v v out = 28v input voltage (v) 5 8 10 14 20 3868 g23 6 4 10 15 25 28 2 0 12 input current (a) temperature (c) ?45 3.4 intv cc voltage (v) 3.5 3.7 3.8 3.9 4.4 4.1 5 55 80 3868 g25 3.6 4.2 4.3 4.0 ?20 30 105 130 oscillator frequency vs input voltage input voltage (v) 5 oscillator frequency (khz) 352 354 356 20 3868 g28 350 348 10 15 25 28 346 344 temperature (c) ?45 frequency (khz) 700 30 3868 g24 400 200 ?20 5 55 100 0 800 600 500 300 80 105 130 freq = intv cc freq = gnd
LTC3868 3868fb p in func t ions sense1 C , sense2 C (pin 1, pin 9): the (C) input to the differential current comparators. when greater than intv cc C 0.5v, the sense C pin supplies current to the current comparator. freq (pin 2): the frequency control pin for the internal vco. connecting this pin to gnd forces the vco to a fxed low frequency of 350khz. connecting this pin to intv cc forces the vco to a fxed high frequency of 535khz. other frequencies between 50khz and 900khz can be programmed using a resistor between freq and gnd. an internal 20a pull-up current develops the voltage to be used by the vco to control the frequency phasmd (pin 3): control input to phase selector which determines the phase relationships between controller 1, controller 2 and the clkout signal. pulling this pin to ground forces tg2 and clkout to be out of phase 180 and 60 with respect to tg1. connecting this pin to intv cc forces tg2 and clkout to be out of phase 240 and 120 with respect to tg1. floating this pin forces tg2 and clkout to be out of phase 180 and 90 with respect to tg1. refer to the table 1. clkout (pin 4): output clock signal available to daisy- chain other controller ics for additional mosfet driver stages/phases. the output levels swing from intv cc to ground. pllin/mode (pin 5): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising tg1 signal to be synchronized with the rising edge of the external clock. when not syn - chronizing to an external clock, this input, which acts on both controllers, determines how the LTC3868 operates at light loads. pulling this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is foated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C 1.3v selects pulse-skipping operation. sgnd (pin 6, exposed pad pin 33): small-signal ground common to both controllers, must be routed separately from high current grounds to the common (C) terminals of the c in capacitors. the exposed pad must be soldered to the pcb for rated thermal performance. intv cc and extv cc vs load current latchoff thresholds vs temperature load current (ma) 0 intv cc voltage (v) 5.10 5.15 5.20 160 3868 g26 5.05 5.00 4.95 20 40 60 80 100 120 140 180 200 extv cc = 0v v in = 12v extv cc = 8v typical p er f or m ance c harac t eris t ics temperature (c) ?45 1.2 intv cc voltage (v) 1.3 1.5 1.6 1.7 2.3 2.2 1.9 5 55 80 3868 g27 1.4 2.0 2.1 1.8 ?20 30 105 130 arming threshold latch-off threshold
LTC3868 3868fb p in func t ions run1, run2 (pin 7, pin 8): digital run control inputs for each controller. forcing either of these pins below 1.26v shuts down that controller. forcing both of these pins below 0.7v shuts down the entire LTC3868, reducing quiescent current to approximately 8a. do not foat these pins. i lim (pin 28): current comparator sense voltage range inputs. tying this pin to sgnd, float or intv cc sets the maximum current sense threshold to one of three different levels for both comparators. intv cc (pin 19): output of the internal linear low dropout regulator. the driver and control circuits are powered from this voltage source. must be decoupled to power ground with a minimum of 4.7f ceramic or other low esr capacitor. do not use the intv cc pin for any other purpose. extv cc (pin 20): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v in whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not exceed 14v on this pin. pgnd (pin 21): driver power ground. connects to the sources of bottom (synchronous) n-channel mosfets and the (C) terminal(s) of c in . v in (pin 22): main supply pin. a bypass capacitor should be tied between this pin and the signal ground pin. bg1, bg2 (pin 23, pin 18): high current gate drives for bottom (synchronous) n-channel mosfets. voltage swing at these pins is from ground to intv cc . boost1, boost2 (pin 24, pin 17): b o otstrapped supplies to the topside floating drivers. capacitors are connected between the boost and sw pins and schottky diodes are tied between the boost and intv cc pins. voltage swing at the boost pins is from intv cc to (v in + intv cc ). sw1, sw2 (pin 25, pin 16): switch node connections to inductors. tg1, tg2 (pin 26, pin 15): high current gate drives for top n-channel mosfets. these are the outputs of foat- ing drivers with a voltage swing equal to intv cc C 0.5v superimposed on the switch node voltage sw. pgood1, pgood2 (pin 27, pin 14): open-drain logic output. pgood1,2 is pulled to ground when the voltage on the v fb1,2 pin is not within 10% of its set point. ss1, ss2 (pin 29, pin 13): external soft-start input. the LTC3868 regulates the v fb1,2 voltage to the smaller of 0.8v or the voltage on the ss1,2 pin. an internal 1a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to fnal regulated output voltage. this pin is also used as the short-circuit latchoff timer. i th1 , i th2 (pin 30, pin 12): error amplifer outputs and switching regulator compensation points. each associ- ated channel s current comparator trip point increases with this control voltage. v fb1 , v fb2 (pin 31, pin 11): receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. sense1 + , sense2 + (pin 32, pin 10): the (+) input to the differential current comparators are normally connected to dcr sensing networks or current sensing resistors. the i th pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold.
LTC3868 0 3868fb f unc t ional diagra m sw 25, 16 top boost 24, 17 tg 26, 15 c b c in d d b clkout pgnd bot bg 23, 18 intv cc intv cc v in c out v out 3868 fd r sense drop out det bot top on s r q q shdn sleep 0.425v icmp 2.7v 0.55v ir 3mv slope comp duplicate for second controller channel sense + 32, 10 sense ? 1, 9 pgood1 v fb1 0.88v 0.72v l 27 21 + ? + ? + ? + ? pgood2 freq v fb2 0.88v 0.72v + ? + ? + ? + ? 14 + ? + ? switch logic v fb 31, 11 r a c c r c c c2 r b 0.80v track/ss 0.88v 0.5a 11v run 7, 8 i th 30, 12 ss 29, 13 + ? c ss 1a 10a shdn current limit foldback shdn rst 2(v fb ) short ckt latch-off 4 phasmd 3 2 pllin/mode 20a vco ldo en intv cc 5.1v sync det 100k c lp clk2 clk1 5 i lim 28 v in extv cc 20 22 ldo pfd en 4.7v 5.1v + ? 19 sgnd 6 ea ov
LTC3868 3868fb o pera t ion (refer to the functional diagram) the LTC3868 uses a constant frequency, current mode step-down architecture with the two controller channels operating 180 degrees out of phase. during normal op - eration, each external top mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the i th pin, which is the output of the error amplifer, ea. the error amplifer compares the output voltage feedback signal at the v fb pin (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage. when the load current increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the i th voltage until the average inductor current matches the new load current. after the top mosfet is turned off each cycle, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, the v in ldo (low dropout linear regulator) supplies 5.1v from v in to intv cc . if extv cc is taken above 4.7v, the v in ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.1v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high effciency external source such as one of the LTC3868 switching regulator outputs. each top mosfet driver is biased from the foating boot - strap capacitor , c b , which normally recharges during each cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period every tenth cycle to allow c b to recharge. shutdown and start-up (run1, run2 and ss1, ss2 pins) the two channels of the LTC3868 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.26v shuts down the main control loop for that controller. pulling both pins below 0.7v disables both controllers and most internal circuits, including the intv cc ldos. in this state, the LTC3868 draws only 8a of quiescent current. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v in ), so long as the maximum current into the run pin does not exceed 100a. the start-up of each controllers output voltage, v out , is controlled by the voltage on the ss pin for that channel. when the voltage on the ss pin is less than the 0.8v internal reference, the LTC3868 regulates the v fb voltage to the ss pin voltage instead of the 0.8v reference. this allows the ss pin to be used to program a soft-start by connecting an external capacitor from the ss pin to sgnd. an internal 1a pull-up current charges this capacitor creating a volt - age ramp on the ss pin. as the ss voltage rises linearly from 0v to 0.8v (and beyond up to the absolute maximum rating of 6v), the output voltage v out rises smoothly from zero to its fnal value. short-circuit latchoff after the controller has been started and been given ad- equate time to ramp up the output voltage, the ss capaci- tor is used in a short-circuit timeout circuit. specifcally, once the voltage on the ss pin rises above 2v (the arming threshold), the short-circuit timeout circuit is enabled (see figure 1). if the output voltage falls below 70% of its nomi- nal regulated voltage, the ss capacitor begins discharg- ing with a net 9a pulldown current on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts long enough to allow the ss pin voltage to fall below 1.5v (the latchoff threshold), the controller will shut down (latch off) until the run pin voltage or the v in voltage is recycled.
LTC3868 3868fb o pera t ion (refer to the functional diagram) the delay time from when a short-circuit occurs until the controller latches off can be calculated using the follow- ing equation: t latch ~ c ss (v ss C 1.5v)/9a where v ss is the initial voltage (must be greater than 2v) on the ss pin at the time the short-circuit occurs. normally the ss pin voltage will have been pulled up to the intv cc voltage (5.1v) by the internal 1a pull-up current. note that the two controllers on the LTC3868 have separate, independent short-circuit latchoff circuits. latchoff can be overridden/defeated by connecting a resistor 150k or less from the ss pin to intv cc . this resistor provides enough pull-up current to overcome the 9a pull-down current present during a short-circuit. note that this resistor also shortens the soft-start period. foldback current on the other hand, when the output voltage falls to less than 72% of its nominal level, foldback current limiting is also activated, progressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. even if a short-circuit is present and the short-circuit latchoff is not yet enabled (when ss voltage has not yet reached 2v), a safe, low output current is provided due to internal current foldback and actual power wasted is low due to the effcient nature of the current mode switching regulator. foldback current limiting is disabled during the soft-start interval (as long as the v fb voltage is keeping up with the ss voltage). light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (pllin/mode pin) the LTC3868 can be enabled to enter high effciency burst mode operation, constant frequency pulse-skip- ping mode, or forced continuous conduction mode at low load currents. to select burst mode operation, tie the pllin/ mode pin to ground. to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when a controller is enabled for burst mode operation, the minimum peak current in the inductor is set to approxi- mately 30% of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifer ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent cu rrent. if one channel is shut down and the other channel is in sleep mode, the LTC3868 draws only 170a of quiescent current. if both channels are in sleep mode, the LTC3868 draws only 300a of quiescent current. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the i th pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. intv cc 2v 0.8v 1.5v 0v 1a ?9a ss voltage latchoff command ss pin current output voltage latchoff enable soft-start interval arming t latch 3868 f01 1a figure 1. latchoff timing diagram
LTC3868 3868fb o pera t ion (refer to the functional diagram) when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator, ir, turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller is in discontinuous operation. in forced continuous operation or when clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin, just as in normal operation. in this mode, the effciency at light loads is lower than in burst mode operation. however, continuous operation has the advantages of lower output voltage ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent of load current. when the pllin/mode pin is connected for pulse-skip- ping mode, the LTC3868 operates in pwm pulse-skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator, icmp, may remain tripped for several cycles and for ce the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference when compared to burst mode operation. it provides higher light load effciency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade off between effciency and component size. low frequency opera - tion increases effciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the LTC3868s controllers can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to sgnd, tied to intv cc or programmed through an external resistor. tying freq to sgnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 9. a phase-locked loop (pll) is available on the LTC3868 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the phase detector adjusts the voltage (through an internal lowpass flter) of the vco input to align the turn-on of controller 1s external top mosfet to the rising edge of the synchronizing signal. thus, the turn-on of controller 2s external top mosfet is 180 degrees out of phase to the rising edge of the external clock source. the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of tg1. the ability to prebias the loop flter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the phase-locked loop is from approximately 50khz to 900khz, with a guarantee over all manufacturing variations to be between 75khz and 850khz. in other words, the LTC3868s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.1v (falling). polyphase ? applications (clkout and phasmd pins) the LTC3868 features two pins (clkout and phasmd) that allow other controller ics to be daisy-chained with the LTC3868 in polyphase applications. the clock output signal on the clkout pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. the phasmd pin is used to adjust the phase of the clkout signal as well as the relative phases
LTC3868 3868fb o pera t ion (refer to the functional diagram) figure 2. input waveforms comparing single-phase (a) and 2-phase (b) operation for dual switching regulators converting 12v to 5v and 3.3v at 3a each. the reduced input ripple with the 2-phase regulator allows less expensive input capacitors, reduces shielding requirements for emi and improves effciency between the two internal controllers, as summarized in table 1. the phases are calculated relative to the zero degrees phase being defned as the rising edge of the top gate driver output of controller 1 (tg1). table 1 v phasmd controller 2 phase clkout phase gnd 180 60 floating 180 90 intv cc 240 120 output overvoltage protection an overvoltage comparator guards against transient over- shoots as well as other more serious conditions that may overvoltage the output. when the v fb pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood1 and pgood2) pins each pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the corresponding v fb pin voltage is not within 10% of the 0.8v reference voltage. the pgood pin is also pulled low when the corresponding run pin is low (shut down). when the v fb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. theory and benefts of 2-phase operation why the need for 2-phase operation? up until the 2-phase family, constant frequency dual switching regulators operated both channels in phase (i.e., single phase operation). this means that both switches turned on at the same time, causing current pulses of up to twice the amplitude of those for one regulator to be drawn from the input capacitor and battery . these large amplitude current pulses increased the total rms current fowing from the input capacitor, requiring the use of more expensive input capacitors and increasing both emi and losses in the input capacitor and battery. with 2-phase operation, the two channels of the dual switching regulator are operated 180 degrees out of phase. this effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where they add together. the result is a signifcant reduction in total rms input current, which in turn allows less expensive input capacitors to be used, reduces shielding requirements for emi and improves real world operating effciency. figure 2 compares the input waveforms for a representa - tive single-phase dual switching regulator to the LTC3868 2-phase dual switching regulator. an actual measurement of the rms input current under these conditions shows that 2- phase operation dropped the input current from 2.53a rms to 1.55a rms . while this is an impressive reduction in itself, remember that the power losses are proportional to i rms 2 , i in(meas) = 2.53a rms i in(meas) = 1.55a rms 3868 f02 5v switch 20v/div 3.3v switch 20v/div input current 5a/div input voltage 500mv/div
LTC3868 3868fb figure 3. rms input current comparison meaning that the actual power wasted is reduced by a fac- tor of 2.66. the reduced input ripple voltage also means less power is lost in the input power path, which could include batteries, switches, trace/connector resistances and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera - tion is a function of the dual switching regulators relative duty cycles which, in turn, are dependent upon the input voltage v in (duty cycle = v out /v in ). figure 3 shows how the rms input current varies for single phase and 2-phase operation for 3.3v and 5v regulators over a wide input voltage range. it can readily be seen that the advantages of 2-phase op - eration are not just limited to a narrow operating range, for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle. o pera t ion (refer to the functional diagram) input voltage (v) 0 input rms current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 20 30 40 3868 f03 single phase dual controller 2-phase dual controller v o1 = 5v/3a v o2 = 3.3v/3a
LTC3868 3868fb a pplica t ions i n f or m a t ion figure 4. sense lines placement with inductor or sense resistor the typical application on the frst page is a basic LTC3868 application circuit. LTC3868 can be confgured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power effcient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. current limit programming th e i lim pin is a tri-level logic input which sets the maximum current limit of the converter. when i lim is grounded, the maximum current limit threshold voltage of the current comparator is programmed to be 30mv. when i lim is foated, the maximum current limit threshold is 50mv. when i lim is tied to intv cc , the maximum current limit threshold is set to 75mv. sense + and sense C pins the sense + and sense C pins are the inputs to the cur- rent comparators. the common mode voltage range on these pins is 0v to 16v (absolute maximum), enabling the LTC3868 to regulate output voltages up to a nominal 14v (allowing margin for tolerances and transients). the sense + pin is high impedance over the full common mode range, drawing at most 1a. this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense C pin changes depending on the common mode voltage. when sense C is less than intv cc C 0.5v, a small current of less than 1a fows out of the pin. when sense C is above intv cc + 0.5v , a higher current (~550a) fows into the pin. between intv cc C 0.5v and intv cc + 0.5v, the current transitions from the smaller current to the higher current. filter components mutual to the sense lines should be placed close to the LTC3868, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 4). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if inductor dcr sensing is used (figure 5b), resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. c out to sense filter, next to the controller inductor or r sense 3868 f04 low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 5a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the current comparator threshold voltage sets the peak of the induc- tor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + ? i l 2 when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability cri - terion for buck regulators operating at greater than 50%
LTC3868 3868fb (5a) using a resistor to sense current (5b) using the inductor dcr to sense current figure 5. current sensing methods a pplica t ions i n f or m a t ion duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak output current depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible effciency at high load currents, the ltc3850 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 5b. the dcr of the inductor represents the small amount of dc resistance of the copper wire, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, power loss through a sense resistor would cost several points of effciency compared to inductor dcr sensing. if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external flter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold voltage (v sense(max) ) in the electrical characteristics table (30mv, 50mv or 75mv depending on the state of the i lim pin). next, determine the dcr of the inductor. when provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coeffcient of copper resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor (r d ) value, use the divider ratio: r r dcr at t d sense equiv max l max = ( ) ( ) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1||r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. v in v in intv cc boost tg sw bg place capacitor near sense pins sense + sense ? sgnd LTC3868 v out r sense 3868 f05a v in v in intv cc boost tg sw bg *place c1 near sense pins inductor dcrl sense + sense ? sgnd LTC3868 v out 3868 f05b r1 r2c1* (r1 || r2) ? c1 = l dcr r sense(eq) = dcr r2 r1 + r2
LTC3868 3868fb a pplica t ions i n f or m a t ion the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: r r l dcr at c c 1 2 20 1 || ? ? ? = ( ) the sense resistor values are: r r r r r r r r d d d 1 1 2 2 1 1 = = || ;?? ? C the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p r v v v r loss in max out out ? C ? ( ) 1 1 = ( ) ensure that r1 has a power rating higher than this value. if high effciency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher effciency at heavy loads. peak effciency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is effciency. a higher frequency generally results in lower effciency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ? i l decreases with higher induc- ta nce or higher frequency and increases with higher v in : i l = 1 f ( ) l ( ) v out 1? v out v in ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.3(i max ). the maximum ?i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran- sition to burst mode operation begins when the average inductor current required results in a peak current below 30% of the current limit determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents, which can cause a dip in effciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high effciency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fxed inductor value, but it is very dependent on inductance value selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfets must be selected for each controller in the LTC3868: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by th e intv cc voltage. this voltage is typically 5.2v during start-up (see extv cc
LTC3868 3868fb a pplica t ions i n f or m a t ion pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 4v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss speci- fcation for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately fat divided by the specifed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specifed v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous s out in ? ? ? ? = wwitch duty cycle v v v in out in ? ? = ? the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1+ ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v thmin + 1 v thmin ? ? ? ? ? ? f ( ) p sync = v in ? v out v in i max ( ) 2 1+ ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current effciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher effciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diodes d1 and d2 shown in figure 10 conduct during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in effciency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection the selection of c in is simplifed by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum rms capacitor current requirement. increasing the out - put current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in conti nuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent
LTC3868 0 3868fb a pplica t ions i n f or m a t ion figure 6. setting output voltage large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/ 2 (1) equation 1 has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3868, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the beneft of the LTC3868 2-phase operation can be calcu - l a ted by using the equation 1 for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall beneft of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the effciency testing. the drains of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the LTC3868, is also suggested. a 10 resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfed, the capacitance is adequate for fltering. the output ripple ( ?v out ) is approximated by: v out i l esr + 1 8 ? f ? c out ? ? ? ? ? ? where f o is the operating frequency, c out is the output capacitance and ?i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. setting output voltage the l tc3868 output voltages are each set by an external feedback resistor divider carefully placed across the out - put, as shown in figure 6. the regulated output voltage is determined by: v out = 0.8v 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. 1/2 LTC3868 v fb v out r b c ff r a 3868 f06 soft-start (ss pins) the start-up of each v out is controlled by the voltage on the respective ss pin. when the voltage on the ss pin is less than the internal 0.8v reference, the LTC3868 regulates the v fb pin voltage to the voltage on the ss pin instead of 0.8v. the ss pin can be used to program an external soft-start function.
LTC3868 3868fb a pplica t ions i n f or m a t ion figure 7. using the track/ss pin to program soft-start soft-start is enabled by simply connecting a capacitor from the ss pin to ground, as shown in figure 7. an internal 1a current source charges the capacitor, providing a linear ramping voltage at the ss pin. the LTC3868 will regulate the v fb pin (and hence v out ) according to the voltage on the ss pin, allowing v out to rise smoothly from 0v to its fnal regulated value. the total soft-start time will be approximately: t ss = c ss ? 0.8v 1a as discussed in the effciency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the LTC3868 intv cc current is limited to less than 45ma from a 28v supply when not using the extv cc supply at 70c ambient temperature: t j = 70c + (45ma)(28v)(43c/w) = 125c to prevent the maximum junction temperature from be- ing exceeded, the input supply current must be checked while operating in forced continuous mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the v in ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.5v. the extv cc ldo attempts to regulate the intv cc voltage to 5.1v, so while extv cc is less than 5.1v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.1v, up to an absolute maximum of 14v, intv cc is regulated to 5.1v. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the LTC3868s switching regulator outputs (4.7v v out 14v) during normal operation and from the v in ldo when the out- put is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc ldo than is specifed, an external schottky diode can be added between the extv cc and intv cc pins. in this case, do not apply more than 6v to the extv cc pin and make sure that extv cc v in . signifcant effciency and thermal gains can be realized by powering intv cc from the output, since the v in cur- rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher effciency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (45ma)(8.5v)(43c/w) = 86c however, for 3.3v and other low voltage outputs, addi- tional cir cuitry is required to derive intv cc power from the output. 1/2 LTC3868 ss c ss sgnd 3868 f07 intv cc regulators the LTC3868 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the v in supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the LTC3868s internal circuitry. the v in ldo and the extv cc ldo regulate intv cc to 5.1v. each of these can supply a peak current of 50ma and must be bypassed to ground with a minimum of 4.7f low esr capacitor. no matter what type of bulk capacitor is used, an additional 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3868 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the v in ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.7v, the v in ldo is enabled. power dissipation fo r the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency
LTC3868 3868fb a pplica t ions i n f or m a t ion figure 8. capacitive charge pump for extv cc the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.1v regulator result- ing in an effciency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v to 14v regulator and provides the highest effciency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc . ensure that extv cc < v in . 4. extv cc connected to an o utput-derived boost network. for 3.3v and other low voltage regulators, effciency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with the capacitive charge pump shown in figure 8. ensure that extv cc < v in . desired mosfet. this enhances the top mosfet switch and turns it on. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the fnal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the effciency has improved. if there is no change in input current, then there is no change in effciency. fault conditions: current limit and current foldback when the output current hits the current limit, the output voltage begins to drop. if the output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from about one-half of its maximum selected value. under short-circuit condi - tions with very low duty cycles, the LTC3868 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time, t on(min) , of the LTC3868 (95ns), the input volt- age and inductor value: i l(sc) = t on(min) v in l ? ? ? ? ? ? the resulting average short-circuit current is: i sc = 50% ? i lim(max) r sense C 1 2 ? i l(sc) fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to fow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the control - ler is operating. extv cc v in tg1 sw bg1 pgnd 1/2 LTC3868 r sense v out vn2222ll c out 3868 f08 mbot mtop c in l d bat85 bat85 bat85 topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate-source of the
LTC3868 3868fb a pplica t ions i n f or m a t ion a comparator monitors the output for overvoltage condi- tions. the comparator detects faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. phase-locked loop and frequency synchronization the l tc3868 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass flter, and a voltage-controlled oscillator (vco). this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the turn-on of controller 2s top mosfet is thus 180 degrees out of phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sourced continu- ously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal flter capacitor, c lp , holds the voltage at the vco input. note that the LTC3868 can only be synchronized to an external clock whose frequency is within range of the LTC3868s internal vco, which is nominally 55khz to 1mhz. this is guaranteed to be between 75khz and 850khz. typically, the external clock (on the pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.1v. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchronization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust the frequency slightly to achieve phase lock and synchronization. although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. table 2 summarizes the different states in which the freq pin can be used. table 2 freq pin pllin/mode pin frequency 0v d c voltage 350khz intv cc dc voltage 535khz resistor d c voltage 50khzC900khz an y of the above external clock phaseClocked to external clock figure 9. relationship between oscillator frequency and resistor value at the freq pin freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3868 f09 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125
LTC3868 3868fb a pplica t ions i n f or m a t ion minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the LTC3868 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v v f on min out in ( ) < ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3868 is approximately 95ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. this is of particular concern in forced continuous applica - tions with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signifcant amount of cycle skipping can occur with cor - respondingly larger current and voltage ripple. effciency considerations the per cent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3868 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc input supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi- cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc from an output-derived power source through extv cc will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(effciency). for example, in a 20v to 5v applica - tion, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis- tor , and input and output capacitor esr. in continuous mode the average output current fows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resis- tance of one mosfet can simply be summed with the resistances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and ou tput capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. effciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system!
LTC3868 3868fb a pplica t ions i n f or m a t ion 4. transition losses apply only to the topside mosfet(s), and become signifcant only when operating at high input voltages (t y pically 15v or greater). transition losses can be estimated from: transition loss = (1.7) ? v in ? 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% effciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. the LTC3868 2-phase architecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr), where esr is the ef- fective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the i th pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac fltered closed-loop response test point. the dc step, rise time and settling at this test point truly refects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in figure 12 circuit will provide an adequate starting point for most applications. the i th series r c -c c flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a resistive load and a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the fltered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de- creasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of
LTC3868 3868fb a pplica t ions i n f or m a t ion c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. design example as a design example for one channel, assume v in = 12v(nominal), v in = 22v (max), v out = 3.3v, i max = 5a, v sense(max) = 75mv and f = 350khz. the inductance value is chosen frst based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. t ie the freq pin to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: ? i l(nom) = v out f ( ) l ( ) 1C v out v in(nom) ? ? ? ? ? ? ? ? a 4.7h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 95ns is not violated. the minimum on-time occurs at maximum v in : t v v f v v khz ns on min out in max ( ) ( ) . = ( ) = ( ) = 3 3 22 350 429 the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (64mv): r sense 64mv 5.73a = 0.01 ? choosing 1% resistors: r a = 25k and r b = 78.1k yields an output voltage of 3.299v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v 5a ( ) 2 1 + 0.005 ( ) 50 c C 25 c ( ) ? ? ? ? 0.035 ? ( ) + 22v ( ) 2 5a 2 2.5 ? ( ) 215pf ( ) ? 1 5v C 2.3v + 1 2.3v ? ? ? ? ? ? 350khz ( ) = 331mw a short-circuit to ground will result in a folded back cur- rent of: i sc = 32mv 0.01 ? C 1 2 95ns 22v ( ) 4.7h ? ? ? ? ? ? = 2.98a with a typical value of r ds(on) and = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = 2.98a ( ) 2 1.125 ( ) 0.022 ? ( ) = 220mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.02(1.45a) = 29mv p-p
LTC3868 3868fb a pplica t ions i n f or m a t ion pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 10. figure 11 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets mtop1 and mtop2 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter- minals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. do the LTC3868 v fb pins resistive dividers connect to the (+) terminals of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing? the flter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur- rent peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposites channels voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC3868 and occupy minimum pc trace area. 7. use a modifed star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller on at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the ap - pl ication. th e frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation thresholdtypically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regula - tor bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly diffcult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter.
LTC3868 3868fb a pplica t ions i n f or m a t ion figure 10. recommended printed circuit layout diagram c b2 c b1 r pu1 pgood1 v pull-up (<6v) c intvcc c in d1 1f ceramic m1 m2 m3 m4 d2 + c vin v out1 v in r in l1 l2 c out1 v out1 gnd v out2 3868 f10 + c out2 + r sense r sense r pu2 pgood2 v pull-up (<6v) f in 1f ceramic i th1 v fb1 sense1 + sense1 ? freq sense2 ? sense2 + v fb2 i th2 ss2 ss1 pgood2 pgood1 tg1 sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 phasmd clkout pllin/mode run1 run2 sgnd LTC3868
LTC3868 3868fb a pplica t ions i n f or m a t ion figure 11. branch current waveforms r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3868 f11 r sense2 v out2 c out2
LTC3868 0 3868fb a pplica t ions i n f or m a t ion reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage.
LTC3868 3868fb typical a pplica t ion s effciency vs output current start-up sw node waveforms figure 12. high effciency dual 8.5v/3.3v step-down converter sense1 + sense1 ? sense2 ? sense2 + v fb1 i th1 sgnd extv cc run1 run2 freq ss2 v fb2 ss1 i lim phsmd clkout pllin/mode pgood1 pgood2 bg1 sw1 boost1 tg1 v in intv cc pgnd tg2 bg2 boost2 sw2 c1 1nf r b1 215k c out1 , c out2 : sanyo 10tpd150m l1: sumida cdep105-3r2m l2: sumida cdep105-7r2m mtop1, mtop2, mbot1, mbot2: vishay si7848dp c f1 15pf c ith1a 150pf c ss1 0.1f c ss2 0.1f c ith1 820pf c int 4.7f c b1 0.47f c b2 0.47f d1 v in 9v to 24v d2 LTC3868 l1 3.3h l2 7.2h r sense1 6m r sense2 8m mbot1 mtop2 mtop1 mbot2 3868 f12 100k 100k intv cc c out1 150f v out1 3.3v 5a v out2 8.5v 3a c in 22f c out2 150f r a1 68.1k r a2 44.2k r b2 422k c f2 39pf r ith1 15k c2 1nf i th2 c ith2 680pf c ith2a 100pf r ith2 27k output current (a) 0.00001 0.0001 40 efficiency (%) 50 60 70 80 0.001 0.01 0.1 1 10 3868 f12b 30 20 10 0 90 100 v in = 12v burst mode operation v out = 8.5v v out = 3.3v 3868 f12c v out2 2v/div v out1 2v/div 20ms/div 3868 f12d sw1 5v/div sw2 5v/div 1s/div
LTC3868 3868fb typical a pplica t ion s sense1 + sense1 ? sense2 ? sense2 + v fb1 i th1 sgnd extv cc run1 run2 freq ss2 v fb2 ss1 i lim phsmd clkout pllin/mode pgood1 pgood2 bg1 sw1 boost1 tg1 v in intv cc pgnd tg2 bg2 boost2 sw2 c1 1nf r b1 143k c out1 , c out2 : sanyo 10tpd150m l1: sumida cdep105-2r5 l2: sumida cdep105-3r2m mtop1, mtop2, mbot1, mbot2: vishay si7848dp c f1 22pf c ith1a 100pf c ss1 0.01f c ss2 0.01f c ith1 820pf c int 4.7f c b1 0.47f c b2 0.47f d1 v in 4v to 24v d2 LTC3868 l1 2.4h l2 3.2h r sense1 6m r sense2 6m mbot1 mtop2 mtop1 mbot2 3868 f13 100k 100k intv cc c out1 150f v out1 2.5v 5a v out2 3.3v 5a c in 22f c out2 150f r a1 68.1k r a2 68.1k r b2 215k c f2 15pf r ith1 22k c2 1nf i th2 c ith2 820pf c ith2a 150pf r ith2 15k high effciency dual 2.5v/3.3v step-down converter
LTC3868 3868fb typical a pplica t ion s high effciency dual 12v/5v step-down converter sense1 + sense1 ? sense2 ? sense2 + v fb1 i th1 sgnd extv cc run1 run2 freq ss2 v fb2 ss1 i lim phsmd clkout pllin/mode pgood1 pgood2 bg1 sw1 boost1 tg1 v in intv cc pgnd tg2 bg2 boost2 sw2 c1 1nf r b1 475k c out1 : kemet t525d476m016e035 c out2 : sanyo 10tpd150m l1: sumida cdr7d43mn l2: sumida cdep105-4r3m mtop1, mtop2, mbot1, mbot2: vishay si7848dp c f1 33pf c ith1a 100pf c ss1 0.01f c ss2 0.01f c ith1 680pf c int 4.7f c b1 0.47f c b2 0.47f d1 v in 12.5v to 24v d2 LTC3868 l1 8.8h l2 4.3h r sense1 9m r sense2 6m mbot1 mtop2 mtop1 mbot2 3858 ta02a 100k 100k intv cc c out1 47f v out1 12v 3a v out2 5v 5a c in 22f c out2 150f r a1 34k r a2 75k r b2 393k c f2 15pf r freq 60k r ith1 10k c2 1nf i th2 c ith2 680pf c ith2a 100pf r ith2 17k
LTC3868 3868fb typical a pplica t ion s sense1 + sense1 ? sense2 ? sense2 + v fb1 i th1 sgnd extv cc run1 run2 freq ss2 v fb2 ss1 i lim phsmd clkout pllin/mode pgood1 pgood2 bg1 sw1 boost1 tg1 v in intv cc pgnd tg2 bg2 boost2 sw2 c1 1nf r b1 28.7k c out1 , c out2 : sanyo 2r5tpe220m l1: sumida cdep105-0r4 l2: sumida cdep105-0r4 mtop1, mtop2: renesas rjk0305 mbot1, mbot2: renesas rjk0328 c f1 56pf c ith1a 200pf c ss1 0.01f c ss2 0.01f c ith1 1000pf c int 4.7f c b1 0.47f c b2 0.47f d1 v in 12v d2 LTC3868 l1 0.47h l2 0.47h r sense1 3m r sense2 3m mbot1 mtop2 mtop1 mbot2 3868 ta03a 100k 100k intv cc c out1 220f 2 v out1 1v 8a v out2 1.2v 8a c in 22f c out2 220f 2 r a1 115k r a2 115k r b2 57.6k c f2 56pf r freq 60k r ith1 3.93k c2 1nf i th2 c ith2 1000pf c ith2a 200pf r ith2 3.93k high effciency dual 1v/1.2v step-down converter
LTC3868 3868fb sense1 + sense1 ? sense2 ? sense2 + v fb1 i th1 sgnd extv cc run1 run2 freq ss2 v fb2 ss1 pllin/mode pgood1 bg1 sw1 boost1 tg1 v in intv cc pgnd tg2 bg2 boost2 sw2 c1 0.1f r b1 28.7k c out1 , c out2 : sanyo 2r5tpe220m l1, l2: vishay ihl p2525czerr47m06 mtop1, mtop2: renesas rjk0305 mbot1, mbot2: renesas rjk0328 c f1 56pf c ith1a 200pf c ss1 0.01f c ss2 0.01f c ith1 1000pf c int 4.7f c b1 0.47f c b2 0.47f d1 v in 12v d2 LTC3868 l1 0.47h l2 0.47h mbot1 mtop2 mtop1 mbot2 3868 ta05 100k r s1 1.18k r s2 1.18k intv cc c out1 220f 2 v out1 1v 8a v out2 1.2v 8a c in 22f c out2 220f 2 r a1 115k r a2 115k r b2 57.6k c f2 56pf r freq 65k r ith1 3.93k c2 0.1f i th2 c ith2 1000pf c ith2a 220pf r ith2 3.93k high effciency dual 1v/1.2v step-down converter with inductor dcr current sensing typical a pplica t ion s
LTC3868 3868fb p ackage descrip t ion uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 p 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 p 0.10 3.45 p 0.10 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 p0.05 3.50 ref (4 sides) 4.10 p0.05 5.50 p0.05 0.25 p 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45o chamfer r = 0.05 typ 3.45 p 0.05 3.45 p 0.05
LTC3868 3868fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 12/09 c hange to absolute maximum ratings c hange to electrical characteristics change to typical performance characteristics change to pin functions text changes to operation section text changes to applications information section change to table 2 change to figure 10 changes to related parts 2 3 6 8 , 9 11, 12, 13 21, 22, 23, 26 23 28 38 (revision history begins at rev b)
LTC3868 3868fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 4 34-0507 www.linear.com ? linear technology corporation 2009 lt 0110 rev b ? printed in usa r ela t e d p ar t s part number description comments ltc3857/ltc3857-1 l o w i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle phase-lockable fixed operating frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a, ltc3858/ltc3858-1 l o w i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle phase-lockable fixed operating frequency 50khz to 900khz, 4v v in 24v, 0.8v v out 14v, i q = 170a, ltc3834/ltc3834-1 l o w i q , synchronous step-down dc/dc controllers phase-lockable fixed operating frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a, ltc3835/ltc3835-1 l o w i q , synchronous step-down dc/dc controllers phase-lockable fixed operating frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 80a, lt3845 l o w i q , high voltage synchronous step-down dc /dc controller adjustable fixed operating frequency 100khz to 500khz, 4v v in 60v, 1.23v v out 36v, i q = 120a, tssop-16 lt3800 l o w i q , high voltage synchronous step-down dc /dc controller fixed 200khz operating frequency, 4v v in 60v, 1. 23v v out 36v, i q = 100a, tssop-16 ltc3824 l o w i q , high voltage dc/dc controller, 100% duty cycle selectable fixed 200khz to 600khz operating frequency, 4v v in 60v, 0.8v v out v in , i q = 40a, msop-10e ltc3850/ltc3850-1 ltc3850-2 du al 2-phase, high effciency synchronous step-down dc/dc controllers, r sense or dcr current sensing and tracking p h ase-lockable fixed o perating frequency 250khz to 780khz, 4 v v in 30v, 0.8v v out 5.25v ltc3855 du al, multiphase, synchronous dc/dc step-down controller with diffamp and dcr temperature compensation p h ase-lockable fixed frequency 250khz to 770khz, 4 . 5v v in 38v, 0.8v v out 12.5v ltc3853 tr iple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 750khz, 4 v v in 24v, v out up to 13.5v ltc3854 s m all footprint wide v in range synchronous step-down dc/dc controller fixed 400khz operating frequency, 4.5v v in 38v, 0. 8v v out 5.25v, 2mm 3 mm qfn-12, msop-12 ltc3775 h i gh frequency synchronous voltage mode step-down dc/dc controller fast t ransient response, t on(min) = 30ns, 4v v in 38v, 0. 6v v out 0.8v in , msop-16e, 3mm 3 mm qfn-16 ltc3851a/ ltc3851a-1 no r sense ? wide v in range synchronous step-down dc/dc controllers phase-lockable fixed operating frequency 250khz to 750khz, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3 mm qfn-16, ssop-16 ltc3878/ltc3879 no r sense constant on-time synchronous step-down dc/dc controllers very fast transient response, t on(min) = 43ns, 4v v in 38v, v out up 90% of v in , msop-16e, 3mm 3 mm qfn-16, ssop-16 ltm4600hv 1 0 a dc/dc module ? complete power supply high effciency, compact size, ultrafast? transient response, 4.5v v in 28v, 0.8v v out 5v, 15mm 1 5mm 2 .8mm ltm4601ahv 1 2 a dc/dc module complete power supply high effciency, compact size, ultrafast transient response, 4. 5v v in 28v, 0.8v v out 5v, 15mm 1 5mm 2 .8mm

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